Modern integrated circuits have billions of discrete elements (e.g. transistors). Terminals of the discrete elements are connected by multi-level wiring. The wiring is one of the elements of the integrated circuits determining an upper limit of clock frequencies of the integrated circuits. The wiring is to be designed in a way that it enables error free propagation of electrical signals synchronized with the clock frequency. This means that electrical signals are to be received at receiving terminals within a time window in a tact interval. The receipt of electrical signals is to be error free. As usual, it requires not only timely receiving of the electrical signals at the receiving terminals but also satisfying a required slew rate of the electrical signals at the receiving terminals.
Modern digital circuitry has tolerances for error free propagation of electrical signals in the picosecond range. The problem of finding an appropriate wiring topology is complicated by the need to connect billions of terminals of the discrete elements. This means that not only propagation of electrical signals in the wiring is to be taken into account but parasitic electromagnetic interactions of electrical signals propagating in adjacent wires are to be taken into account as well. The last but not least problem is that a complete performance of the wiring can be calculated only when the wiring topology is completely generated. As a consequence, a process of generation of the wiring topology is performed as usual just using simple design rules being primarily derived from constraints of an integrated circuit manufacturing process. Thus, there is a need to improve the process of the generation of the wiring topology.